1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to thermal management structures for stacked semiconductor chips and to methods of assembling the same.
2. Description of the Related Art
Many current integrated circuits are formed as multiple dice on a common wafer. After the basic process steps to form the circuits on the dice are complete, the individual die are singulated from the wafer. The singulated die are then usually mounted to structures, such as circuit boards, or packaged in some form of enclosure.
One frequently-used package consists of a substrate upon which a die is mounted. The upper surface of the substrate includes electrical interconnects. The die is manufactured with a plurality of bond pads. A collection of solder joints are provided between the bond pads of the die and the substrate interconnects to establish ohmic contact. After the die is mounted to the substrate, a lid or other form of heat spreader is placed in thermal contact with the die. Many conventional integrated circuits generate sizeable quantities of heat that must be transferred away to avoid device shutdown or damage. A lid heat spreader serves as both a protective cover and a heat transfer pathway.
To provide a heat transfer pathway from the integrated circuit to the lid, a thermal interface material is placed on the upper surface of the integrated circuit. In an ideal situation, the thermal interface material fully contacts both the upper surface of the integrated circuit and the portion of the lower surface of the lid that overlies the integrated circuit. Conventional thermal interface materials include various types of pastes, and in some cases, a metal. Gel-type thermal interface materials consist of a polymeric matrix interspersed with thermally conductive particles, such as aluminum. More recently, designers have begun to turn to solder materials as a thermal interface material, particularly for high power-high temperature chips.
A solder thermal interface material like indium has favorable thermal properties that work well for high power-high temperature die. However, indium exhibits relatively poor adhesion to silicon. To facilitate bonding with indium, the backside of a silicon die may be provided with a metallization stack that includes a layer that readily adheres to silicon, a layer that readily wets indium and perhaps one or more intermediary barrier or other layers. An entire wafer of dice may be provided with respective metallization stacks en masse prior to dicing. To establish favorable thermal contact between a conventional solder thermal interface material and the semiconductor chip and lid that bracket it, a reflow process is performed to wet the applicable surfaces.
Stacked semiconductor chip devices present a host of design and integration challenges for scientists and engineers. Common problems include providing adequate electrical interfaces between the stacked semiconductor chips themselves and between the individual chips and some type of circuit board, such as a motherboard or semiconductor chip package substrate, to which the semiconductor chips are mounted. Another critical design issue associated with stacked semiconductor chips is thermal management. Most electrical devices dissipate heat as a result of resistive losses, and semiconductor chips and the circuit boards that carry them are no exception. Still another technical challenge associated with stacked semiconductor chips is testing. Stacked dice present an additional technical challenge for integration of both solder and organic thermal interface materials. A stacked dice arrangement is non-planar relative to the underlying package substrate, yet thermal contact between the solder thermal interface material, each chip and the heat spreader is often desired. The non-planarity can lead to inadequate thermal pathways to dissipate heat from the lowermost chip in the stack. This can limit the power and size for the lowermost die.
From a circuit design and performance perspective, it makes sense to place a high heat dissipating die, such as a processor, in a lower position in a 3D stack and thereafter stack lower heat dissipating dice, such as memory devices, on the lower die. Thermal management of this arrangement presents challenges. Thermal management of a semiconductor chip or chips in a stacked arrangement remains a technical challenge during normal operation and required electrical testing of one or more of the semiconductor chips. A given semiconductor chip in a stacked arrangement, whether the first, an intermediary or the last in the particular stack, may dissipate heat to such an extent that active thermal management is necessary in order to either prevent the one or all of the semiconductor chips in the stack from entering thermal runaway or so that one or more of the semiconductor chips in the stack may be electrically tested at near or true operational power levels and frequencies.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.